3. Confirm Specifications

3.1. Confirm Main Processor Specifications

  • Supported upper limit of Combo PHY input frequency.

  • Supported Combo PHY lane configuration.

  • Supported linear/WDR interface modes.

  • Supported I2C bus number.

  • Supported output reference clock.

For example, cv181x supports the following:

  • 1C4D（1clk lane，4data lane）

  • 2.5Gbps/lane

  • RAW(8/10/12)+YUV422(8/10)

  • 2-frame HDR (180X no support WDR)

  • Support lane/pn swap

  • I20-I2C3

  • 200 – 600M MAC clock:

    _images/Confir002.png

    Mclk reference clock:

    _images/Confir003.png

3.2. Confirm Sensor Specifications

  • Confirm Sensor Control Interface (I2C/SPI).

_images/Confir004.png

  • Confirm Sensor Power-on Sequence.

_images/Confir005.png

  • Confirm sensor input reference clock.

  • Confirm Bayer pattern and pixel code width.

_images/Confir006.png

  • Confirm the image transfer interface mode and output frequency for linear/WDR mode.

_images/Confir007.png

  • Confirm how to set exposure time and gain for linear/WDR mode.

  • Confirm how to modify frame rate for linear/WDR mode.

  • Confirm the sync code when the interface is subLVDS/HiSPi.

  • Request Sensor Initialize Settings from the sensor manufacturer.